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mipi csi2 dphy registers

Question asked by Fan Al on May 5, 2016
Latest reply on May 5, 2016 by igorpadykov

Could you explain me some points related to MIPI_CSI_PHY_STATE in imx6.


First of all 9-th bit. Active low. Is that mean that clk lane in ULPS if the bit equal zero value?


8-th bit. Clock lane actively receiving a DDR cloclk. Is that bit mean(1-value) that imx6 DPHY module clock is correctly configured. In my case it is always zero value.