Recently NXP changed revision of the LPC2300/2400 families from Rev B to Rev D. This main implication of this change are summarized in the ES for the parts:
“On the LPC23XX/LPC24XX Rev D, design changes to the Memory Accelerator Module were made to enhance timing and general performance. Design changes are intended to enhance performance in general and will result in minor differences in the code execution timing between the previous device revisions and rev D. Actual performance impact is code dependent, some code sequences may speed up while other code sequences may slow down between the previous device revisions and rev D. This might be observed when using software delays and in such cases, a hardware timer should be used to generate a delay instead of a software delay.”
One other side effect that has been noticed by some customers is related to Ethernet operation in RMII mode when using the National Semiconductor DP83848 PHY.
In all cases it appears that the issue is related to the incorrect Ethernet PHY connection to the LPC device. The National Semiconductor Application note “AN-1405 - PHY in RMII mode” clearly states in Table 2:
"The 25MHz_OUT signal is a delayed version of the X1/REF_CLK input. While this clock may be used for other purposes, it should not be used as the timing reference for RMII control and data signals."
In summary, the 25MHz_OUT should not be used for LPC device ENET_REF_CLK signal.
The error in schematics may be attributed to a third party design that has since been fixed but some users have the incorrect design and thus in some cases using the Rev D with the DP83848 PHY, Ethernet does not work reliably.