the T1040RM listed a CKSTP_OUT_B pin but the e5500 said "The e5500 does not take a checkstop, as is the case with previous e500 cores." what are the conditions that will cause the checkstop out pin to be asserted?
Checkstop functionality is used for debug purposes only.
The EVT signals can be used to generate checkstop in the T104x device.
I understand that checkstop is no longer associated with machine check exception in the e5500. But I would like to know what will cause the checkstop out pin CKSTP_OUT_B to be asserted?
> The EVT signals can be used to generate checkstop in the T104x device.
> what will cause the checkstop out pin CKSTP_OUT_B to be asserted?
Please explain why you pose this question?
In the traditional PowerPCs, machine check was tied to checkstop. Now it no longer does. I found this reference for the P4080:
“The DACRDn, as well as DACREn and DACRRn registers along with CKSTPCR will determine what events can cause the CKSTP_OUT_N pin to be asserted.”
I would like to know the same thing for the T104x.
We are using checkstop in our software and would need to know what changes we need to make to accommodate for checktop not being there anymore. Or if there are ways we can still generate checkstop.
Excuse me, but it has alredy been written:
> Checkstop functionality is used for debug purposes only.
This means that checkstop functionality can't be used during normal processor operation.
Sorry, but additional information is available only for debug tools vendors.
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