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K02 Clock Manager Setup

Question asked by An Bui on May 2, 2016
Latest reply on May 9, 2016 by David E Seymour

Our design is using an 16 Mhz external crystal for the K02.

 

I'm setting the clock manger for SystemCoreClock = 80000000 (80 MHz) with the following parameters:

const clock_manager_user_config_t g_defaultClockConfig =

{

    .mcgConfig =

    {

        .mcg_mode           = kMcgModeFEE,

        .irclkEnable           = true,  // MCGIRCLK enable.

        .irclkEnableInStop  = false, // MCGIRCLK disable in STOP mode.

        .ircs               = kMcgIrcSlow, // Select IRC32k.

        .fcrdiv             = 0U,    // FCRDIV is 0.

 

        .frdiv   = 4U,

        .drs     = kMcgDcoRangeSelLow,  // Low frequency range

        .dmx32   = kMcgDmx32Default,    // DCO has a default range of 25%

        .oscsel  = kMcgOscselOsc,       // Select OSC

#if FSL_FEATURE_MCG_HAS_PLL1  /* There are NO PLL on K02 */

        .pll0EnableInFllMode        = false,  // PLL0 disable

        .pll0EnableInStop           = false,  // PLL0 disalbe in STOP mode

        .prdiv0                     = 0x1U,

        .vdiv0                      = 0x6U,

#endif

    },

    .simConfig =

    {

     .pllFllSel = kClockPllFllSelFll,

     .er32kSrc  = kClockEr32kSrcOsc0,

        .outdiv1   = 0U,

        .outdiv2   = 1U,

        .outdiv3   = 3U,

        .outdiv4   = 4U,

    },

    .oscerConfig =

    {

        .enable       = true,  // OSCERCLK enable.

        .enableInStop = false, // OSCERCLK disable in STOP mode.

        .erclkDiv     = 0U,    // OSCERCLK divider setting.

    }

};

 

Our UART driver module is not reading the proper characters from our device.  This configuration is from the K02 Reference Manual.

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