I'm working with a FRDM-K64K board, and KDS 3.0.1 and KSDK 2.0 environment.
I have not a great experience on this environment, so the question could be
obvious for expert guys.
I need to generate a clock signal and connect it to a GPIO output on the FRDM-K64K board.
This GPIO output will be used as the XCLK signal to a device (an AFE032 Power-Line
Communications AFE), available on an external module.
I plan to use the PIT driver, configure it to the requested frequency and set up the GPIO
in the interrupt function of the PIT.
Do you think there is a better, or simplest solution to do so ?
Thanks for your help,