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Performance issue about Cortex-CM4 of i.MX6 SoloX

Question asked by Guohu Xu on Apr 28, 2016
Latest reply on Jun 7, 2016 by igorpadykov

Hi NXP experts,

 

When I developing on i.MX6 SoloX, I found confusing scenario on the performance of reading/writing memory when cache is enable.

Following are my test results which measure the number of read, write or both read and write of memory access in 1 seconds for SoloX and Vybrid:

 

Cache enable

--------------------------------------------------+--------------------+-------------------+

Operation type                                    |     SoloX data     |     Vybrid data   |

--------------------------------------------------+--------------------+-------------------+

Large Array Read&Write with 4-byte interleave     |      4929846       |        7102300    |

--------------------------------------------------+--------------------+-------------------+

Large Array Read with 4-byte interleave           |      15981136      |        9388063    |

--------------------------------------------------+--------------------+-------------------+

Large Array Write with 4-byte interleave          |      11219092      |        9742647    |

--------------------------------------------------+--------------------+-------------------+

Large Array Read&Write with cache line interleave |      3224001       |        2894259    |

--------------------------------------------------+--------------------+-------------------+

Large Array Write with cache line size interleave |      10966110      |        2937975    |

--------------------------------------------------+--------------------+-------------------+

Large Array Read with cache line size interleave  |      6235732       |        3746016    |

--------------------------------------------------+--------------------+-------------------+

 

Cache disable

--------------------------------------------------+--------------------+-------------------+

Operation type                                    |     SoloX data     |     Vybrid data   |

--------------------------------------------------+--------------------+-------------------+

Large Array Read&Write with 4-byte interleave     |      1275320       |        790198     |

--------------------------------------------------+--------------------+-------------------+

Large Array Read with 4-byte interleave           |      1505184       |        927335     |

--------------------------------------------------+--------------------+-------------------+

Large Array Write with 4-byte interleave          |      1778737       |        1112651    |

--------------------------------------------------+--------------------+-------------------+

Large Array Read&Write with cache line interleave |      1275292       |        790146     |

--------------------------------------------------+--------------------+-------------------+

Large Array Write with cache line size interleave |      1778841       |        1112651    |

--------------------------------------------------+--------------------+-------------------+

Large Array Read with cache line size interleave  |      6235732       |        3746016    |

--------------------------------------------------+--------------------+-------------------+

 

The frequency of SoloX is 227MHz, while Vybrid is 166MHz.

The 4-byte interleave means 1 cache miss followed by 7 cache hits.

While cache line size(32 bytes) interleave means cache miss for every access.

The performance of SoloX is better than that of Vybrid for most items, it's reasonable because it has higher frequency.

But when doing both read and write with 4-byte interleave in the iteration, the performance of SoloX is worse than Vybrid.

However, when the interleave is cache line size(32 bytes), the performance data looks fine.

 

I want to know is there any reasonable explanation about the worse performance for SoloX when doing memory read and writing access with high cache hit rate(about 7/8)?

Is there any configuration that would affect this?

Thanks.

 

Best Regards,

Guohu

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