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Need urgent help - P1013 JTAG and Bank 0 access not working

Question asked by Amit Khanna on Apr 28, 2016

I have a board with P1013 processor and need urgent help resolving issue below.

 

I have setup the BOOT option for LB FCM 8-bit NAND Flash Small page. 

CKSTP_OUT0_N = '1' (4.7K pull-up boot strap)

CKSTP_OUT1_N = '0' (4.7K pull-down boot strap)

ETH_PHY_TXD1 = '0' (4.7K pull-down boot strap)

GPP_READY_P0 = '0' (4.7K pull-down boot strap)

 

When accessing the device via JTAG, I get an error.  See attachment.  Please help me understand why required boot strapping pull-down on CKSTP_OUT1_N is causing error on JTAG.

 

If I remove the pull-down on CKSTP_OUT1_N, I am able to access the device via JTAG.

 

After accessing the JTAG any, we tried to access Bank 0 as we have NAND flash connected to Bank 0.  However, it fails. That is, I don't see any activity on Chip Select 0, Write enable, output enable on FCM interface.  However, when I access Bank 1, i see activity on all the signals.  Please help me understand what setting am I missing to Bank 0 access.

 

Following is how we are configured the registers in regards to FCM/NAND Flash

 

#define CONFIG_NAND_ADDR_BOOT 0xEFF00000

 

   // LAWBAR6 - Local Bus NAND (boot)
   //   bit 8 - 31 = 0xEFF00000 - base addr
   MM_LAWBAR6 = CONFIG_NAND_ADDR_BOOT >> 12;
   
   // LAWAR6
   //   bit 0 = 1 - enable window
   //   bit 7-11 = 00100 - Local Bus
   //   bit 26-31 = 001111 64k - size
   MM_LAWAR6 = 0x8040000f;

 

   // CS0 - NAND Flash (boot)  
   //   BR0 base address at 0xEFF00000, port size 8 bit, FCM
   eLBC_BR0 = 0xf8001001;
   //   OR0 64KB flash size, FCM (large page NAND Flash)
   eLBC_ORf0 = 0xf8000ff7;

 

Regards,

Amit

Original Attachment has been moved to: target-init-fail.txt.zip

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