Hi,
I would like to output data on a SPI bus using DMA using the M4 processor of the Vybrid processor. The data going to the SPI would be from a memory buffer. The SPI was initiallized using normal MQX functions and verified to function before trying to switch to using the DMA. When CSR = 1 is run, the DMA appears to go through its process and CSR then is set to 0x80 and no errors are shown in DMA1.ERR or DMA1.ES. It appears that the FIFO on the SPI are filled with the data, but no data appears to be sent out from the SPI pins.
Sample Source:
| #define | SIZE8 0 |
| #define | SIZE16 1 |
#define SIZE32 2
//Enable DMA CH Mux1 Clock
CCM_CCGR0 |= CCM_CCGR0_CG5(3);
//DMA1
CCM_CCPGR3 |= CCM_CCPGR3_PPCG8(3) | CCM_CCPGR3_PPCG9(3);
//Enable SPI 2 source for DMA1
DMAMUX2_CHCFG0 = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(11);
SPI2_RSER |= 0x03000000; //Enable DMA request for TFFF (transmit buffer fill flash)
DMA1_TCD0_SADDR = (uint32_t)(writeData.data); //Source Address For Transfer
DMA1_TCD0_ATTR = DMA_ATTR_SMOD(0) | DMA_ATTR_SSIZE(SIZE16) //Modulo and access size for source
| | | | | DMA_ATTR_DMOD(0) | DMA_ATTR_DSIZE(SIZE16);//and destination |
DMA1_TCD0_SOFF = 2; //source address offset in bytes after each access
DMA1_TCD0_NBYTES_MLNO = DMA_NBYTES_MLNO_NBYTES(writeData.dataSize); //total number of bytes in minor loop (is a multiple of 16 bits)
DMA1_TCD0_SLAST = (writeData.dataSize * -1); //source address adjustment on major loop completion - used to reset TCD
DMA1_TCD0_DADDR = (uint32_t)(&SPI2_PUSHR); //Destination Address For Transfer
DMA1_TCD0_CITER_ELINKNO = 1; //current major count
DMA1_TCD0_DOFF = 0; //destination address offset in bytes after each access
DMA1_TCD0_DLASTSGA = 0; //destination address adjustment on major loop completion - used to reset TCD
DMA1_TCD0_BITER_ELINKNO = 1; //total major iteration count
DMA1_TCD0_CSR = 0; //set all bits to zero
DMA1_SERQ = 0; //set TCD0 enable
DMA1_TCD0_CSR = 1; //start the DMA
Thanks for any help,
Dan K.
