Our partner have a question about i.MX6 DDR layout.
Please see chapter 3.6 of Hardware Development Guide (IMX6DQ6SDLHDG Rev.1)
It mentions about decoupling and bulk capacitors for VTT island, but not mention about its layout.
Would you let me know the recommended layout of decoupling and bulk capacitors for VTT?
(e.g. xx mils trace between decoupling cap and yyy)
About the number of capacitors, its says "Place one or two 0.1 μF decoupling capacitors by each termination RPACK on the VTT".
What is RPACK?