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How to configure ssi1_clk and clko_clk when used as i2s master sclk and mclk?

Question asked by zero zero on Apr 24, 2016
Latest reply on Apr 24, 2016 by zero zero

Dear Sir or Madam,


                The default code I find ssi1_clk parent is pll3_pfd_508M and clko_clk parent is pll2_528_bus_main_clk that kernel version is 3.0.35.  In order to meet the requirements of master I2S , do I need to modify the clock parent?

                 I don't really understand the difference between the clock, such pll3_pfd_508M and pll2_528_bus_main_clk. Apart from the frequency and frequency of different multiples, what is the difference?

                 Now I set the parent clk for ssi1_clk and clko_clk to pll4, but I find I can't modify clko_clk and ssi1_clk less than 24mhz no matter how to change pll4 clock. 

                  Do you have any known ways to achieve this?