My platform is imx6ul. spi clk is 40M
I changed SPI dma dst_maxburst to spi_imx_get_fifosize(spi_imx) and sent about 1KB to measure timing.
Bellow is one burst (64 bytes) timing and with some delay and then is the next burst(64 bytes).
the whole wave is:
My question is: what cause the delay between every burst?
I notice there is risc processor to deal with sdma and fsl provide firmware.
So I guest that once the driver attach one dma request, then the firmware write data out and then read received data, that is, the delay between burst write operation is the time that read operation cost. Is it right?
And a another question is: how to reduce the delay between burst?
Thank you for your suggesion.