Meaning of PCIe RC reg RESR error Multiple ERR_COR Received

[shefft]

iMX6SDL, single core

In the RC mode register RESR at 1FF_C130h I'm seeing a multiple ERR_COR Received being reported, but what does that mean and how can I trouble shoot?  This error does not appear with the same HW running the working Linux pcie driver (and endpoint).  The PL DEBUG1 register shows xmlh_training_rst_n LTSSM-negotiated link reset is set, continually.

[igorpadykov]

Hi Tyler

error is described in sect.48.3.5.2 PCIe Baseline Capability  i.MX6DQ RM

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

Reporting of errors by a downstream port to the RC is achieved by sending an error message. The decision

to send an error message is controlled by a complex set of associated control and status bits. For more

details, see the flow diagram in Section 6.2.6, “Error Message Controls” of the PCI Express Base 3.0

Specification, revision 1.0. Messages sent to the RC are of the ERR_CORR, ..

Best regards

igor

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