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maximum delay between the write into the ECSPIx_CONFIGREG register and the change of SCLK polarity

Question asked by yuuki on Apr 20, 2016
Latest reply on Apr 21, 2016 by Artur Petukhov

Dear all,

 

We are porting of Linux to our i.MX6 solo board to a base in Linux L3.10.53 BSP.

In our system, Flash and RTC are connected to SPI.

 

The device connected to SSx of SPI is the following.
SS0: Flash 200MHz
SS1: Flash 200MHz
SS2: RTC 20MHz

 

With switches from SS2 to SS0, we found SCLK polarity changing after GPIO chipselect was asserted.

We found the following patch about SPI.

http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=6fd8b8503a0dcf66510314dc054745087ae89f94

 

The contents of this patch are included in Linux L3 .10.53 BSP.
However, this problem does not seem to be solved.

 

According to Explanation of this patch, the following is explained.
"Therefore, the time it takes for the write to ECSPIx_CONFIGREG to take effect in the hardware is up to the duration of 1 tick of the SCLK clock."

 

For i.MX6, it seems that the delay time is bigger than 1 tick of the SCLK clock.

 

Would you tell me the maximum delay between the write into the ECSPIx_CONFIGREG register and the change of SCLK polarity?

 

 

 

It it is the setting that SCLK polarity is not changed, a glitch occurs on SCLK.
https://community.freescale.com/thread/386935

 

Best Regards,
Yuuki

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