If the P1011 is forced to undergo a reset, does this bring down an active PCIe link? If so, does the link need to be re-established as if it were starting over from a power-on condition? Does this hold true for RC and EP operations?
Please consider that all the SOC registers (including ATMU) are reset in the described case.
What if the unit on the other end of the PCIe from the P1011 goes through a reset and the link comes down. How does the P1011 know when to re-establish the link (assuming it is the RC)?
At the physical level the link is re-trained automatically and no software involvment is needed.
At the system level attempt to access previously enumerated resource will generate an exception wich has to be processed by an OS and the PCI bus has to be re-enumerated.
Thank you for this insight. I am curious how long the link hardware will try to re-train the PCIe before it gives up. Some worst case reset/loss and reboot processes can take a while (minutes not seconds), especially if power-up self tests are executed prior to enabling the application. This may be an area worth exploring via testing.
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