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i.MX 6UltraLite and external clock for ENET

Question asked by Piotr Piwko on Apr 16, 2016
Latest reply on May 17, 2016 by li chao

Hi,

 

I'm trying to bring up the Enet1 subsystem of custom board. We use LAN8720 phy chip which should provided reference clock. From electrical point of view it seems that we have everything all right: 25MHz signal from external oscillator connected to LAN8720 and 50MHz signal on the output connected to ENET1_TX_CLK pad.

 

I'm working with uboot-imx v2015.04_3.14.38_6ul_ga code and basing on IMX6UL EVK, I made following modifications:

1) Set correct CONFIG_DEF_ENET_DEV to 0x0

2) Set CONFIG_FEC_MXC_PHYADDR to 0x0

3) Set ENET1_CLK_SEL bit in IOMUXC_GPR_GPR1

4) Clear ENET1_TX_CLK_DIR bit in IOMUXC_GPR_GPR1

5) Use MX6_PAD_ENET1_TX_CLK_ENET1_TX_CLK mux instead of MX6_PAD_ENET1_TX_CLK_ENET1_REF_CLK1

 

After those steps I'm able to read PHY registers via MDIO, but I'm not able to send/receive packets via RMII (timeout on fec_send() and empty buffer in fec_recv()). I was checking all relevant registers and they look ok, so probably I missed something.

 

Did you try to use external clock for Enet subsystem on this CPU? Cloud you please give me some advice what can be wrong?

 

Thank you in advance for your engagement.

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