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Enabling TZASC on LS1021a

Question asked by Siles on Apr 14, 2016
Latest reply on Apr 29, 2016 by Siles

Hi !

I'm trying to enable the TZASC (TZC380) of my QorIQ LS1021a board, in order to protect the end of the DDR from the normal world. My setup is the following (I'm using NXP SDK v1.9):

- the board boots on the SD card, loading the SPL on the on-chip ram. The SPL performs the switch to the normal world before starting u-boot.img, which will start Linux.

If I don't active TZASC nor SMMU, everything is fine (I patched u-boot so that all access to secure only registers/resources are done in the SPL, not in u-boot)

 

In order to activate the TZASC, I do the following:

- In the SPL, before DDR is configured, I initialize the TZASC by attributing 3/4 of the DDR to normal world (0x8000_0000 -> 0xb000_0000) and 1/4 to the secure world (0xb000_0000 -> 0xc000_0000)

- I set the ICID for the peripheral in the SCFG component

- In the SMMU1, I configure the SSD space so that peripherals are Secure

- I flip the TZASC activation bit in the CSU

SPL is doing find and manages to copy u-boot in normal DDR, and jumps to u-boot. Then u-boot starts to run correctly, but seems to hang at some point.

 

I'm actually investigating if I need to configure the other SMMU of the boards in order for u-boot to launch Linux or if it is not necessary. But this is my first time configuring a TZASC so I might have forgotten an important step, especially in the SMMU configuration.

 

Any help/advice is welcome.

Here is the log up to the hanging part:

U-Boot 2015.01+SDKv1.9+g555decd (Apr 13 2016 - 14:10:20)

CPU:   Freescale LayerScape LS1021E, Version: 2.0, (0x87081120)
Clock Configuration:
       CPU0(ARMV7):1000 MHz, 
       Bus:300  MHz, DDR:800  MHz (1600 MT/s data rate), 
Reset Configuration Word (RCW):
       00000000: 0608000a 00000000 00000000 00000000
       00000010: 30000000 00007900 60040a00 21046000
       00000020: 00000000 00000000 00000000 20000000
       00000030: 00080000 881b7340 00000000 00000000
Board: LS1021ATWR
CPLD:  V2.0
PCBA:  V1.0
VBank: 0
I2C:   ready
DRAM:  768 MiB
Using SERDES1 Protocol: 48 (0x30)

The next line should be

Using SERDES1 Protocol: 48 (0x30)

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