Using a FRDM-KL27Z developed LPUART and IIC driver driver code that works great.
- Using KEIL, MDK-Lite Version 5.18 with CMSIS version 4.3.0
- Using SWD to program/debug.
- Programming using the PE Micro Multilink Universal FX.
However, our production intent target MCU is the KL17Z256.
- Replaced the KL27Z64VLH4 on the FRDM-KL27Z with the KL17Z256LH4.
- Created new uVision project specifying the KL17Z256 as the target.
- Copied code changing only the headers.
Result is no working LPUART1 or I2C1 (currently the only modules tested).
- Stripped the code down to initializing the LPTMR and LPUART1.
- Testing TX in a loop with scope probe.
- LPTMR works fine.
- TX is always LOW (no data transferred).
- LPUART_STAT_TDRE is set, but no data is actually transferred.
- This exact code (minus the device header and associated CMSIS ) works great.
- Tested on (3) different KL17Z256LH4 same result.
- (1) of the KL17Z256LH4 was on our own board never touching the FRDM-27Z.
- Tried programming using PE Micro and CMSIS-DAP, same result.
- GPIO toggling on the TX pins works fine.
- Similar issue with I2C1 as well on KL17 (no data transferred)
SDA always HIGH, SCL does pull LOW but no CLOCK. - Tried different internal clock option (48MHz and 8MHz), currently do not have an external crystal.
Some thoughts on what could be missing?
I feel like maybe a missed register not properly set to default?
- Do not want to use Processor expert.
- Prefer bare metal CMSIS code base.
// CODE USED (Works on KL27Z after replacing the device header)
#include "MKL17Z4.h" // Device header
void LPTMR_init(void);
void LPTMR_delay(unsigned int length_ms);
int main()
{
// Initialize the LPTMR
LPTMR_init();
// Clock Configuration
MCG_C1 |= MCG_C1_CLKS(1); // Internal reference clock IRC8M
MCG_C2 |= MCG_C2_IRCS_MASK; // Fast internal reference clock selected,8MHz
MCG_SC = 0x0; // FCRDIV = 8M/1
LPTMR_delay(10);
SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV1(0) | // Core clock 8M/1
SIM_CLKDIV1_OUTDIV4(0); // Bus clock 8M/1/1
SMC_PMPROT = SMC_PMPROT_AVLP_MASK; // Allow VLPR, VLPW and VLPS
SMC_PMCTRL = SMC_PMCTRL_RUNM(0); // Normal run
// Enable Clock Gating on PORTC for LPUART1 TX
SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
// Set the MUX LPUART1 TX
PORTC->PCR[4] = PORT_PCR_MUX(3);
// Set the clock source
SIM->SOPT2 |= SIM_SOPT2_LPUART1SRC(1);
// Enable LPUART Module
SIM->SCGC5 |= SIM_SCGC5_LPUART1_MASK;
// Disable TX and RX while configuring
LPUART1->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
// Baud Register Options
// 9600 with 8 MHz clock
LPUART1->BAUD = LPUART_BAUD_OSR(0x03)
| LPUART_BAUD_SBR(0xD0)
| LPUART_BAUD_BOTHEDGE_MASK;
// Control Register Options
LPUART1->CTRL = 0;
// Stat Register Options
LPUART1->STAT = 0;
// Enable TX and RX
LPUART1->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK;
while(1)
{
// Wait until space is available in the FIFO
while(!(LPUART1->STAT & LPUART_STAT_TDRE_MASK));
// Send a test character
LPUART1->DATA = 0xA5;
// Delay 100ms
LPTMR_delay(100);
}
return 0;
}
void LPTMR_init(void)
{
// Turn on clock gate for the LPTMR
SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
// Set up LPTMR to use 1kHz LPO with no prescaler as its clock source
LPTMR0->PSR = LPTMR_PSR_PCS(1) | LPTMR_PSR_PBYP_MASK;
}
void LPTMR_delay(unsigned int length_ms)
{
// Clear settings
LPTMR0->CSR = 0;
// Compare value (ms) based on 1 kHz LPO
LPTMR0->CMR = length_ms;
// Start the timer
LPTMR0->CSR |= LPTMR_CSR_TEN_MASK;
// Wait for counter to reach compare value
while (!(LPTMR0->CSR & LPTMR_CSR_TCF_MASK));
// Disable counter and Clear Timer Compare Flag
LPTMR0->CSR &= ~LPTMR_CSR_TEN_MASK;
}
Original Attachment has been moved to: main.c.zip
Correction to initial discussion