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Problems with I.MX6Q calibration in Uboot

Question asked by Andy Ho on Apr 13, 2016
Latest reply on Apr 13, 2016 by Andy Ho

Hi,

 


We have a imx6q custom board with 2xLPDDR2 memories, the boot_mfg is configured as fix 2x32 lpddr2,

MMDC0 CS0, CS1/MMDC1 CS0 CS1 are all used.

 

I have found the hw auto calibrations (ZQ, Write leveling, read dqs, read delay,write delay) are implemented in new uboot SPL, and follow Imx6 DDR calibration sample code, so I ready to modify it for my project.
First, I think 2x32 mode is different from x64, all the calibrations must be done for MMDC0 and MMDC1 independently,  The code is implement for x32/x64 mode, so I modify and test the uboot code by add same code for MMDC1 , but it can only work for MMDC0, but fail to work for MMDC1.

 

My problems are:

 

1. Which calibration is neccesary for LPDDR2 (ZQ, Write leveling, read dqs, read delay,write delay)?
   If you check reference manual, for example, write leveling calibration should be disable in lpddr2 mode, but the related registers can be configured for lp2_2ch_x32? or Read DQS calibration is neccesary for read/write delay calibration, but the related registers are only for DDR3 x32/x64?

 

2. Can we use same MMDC0 calibration code for MMDC1 in lpddr2 2x32 mode? if yes, I don't know why it always fail during MMDC1 calibration.

 

3. MMDC1 ZQ calibration not perform:
   As you can see the result, ZQ calibration can be done for MMDC0, but not work for MMDC1. In reference manual, MMDCx_MPZQHWCTRL is only for channel 0, channel1 ZQ calibration is also control by MMDC0 , so don't know how to perform MMDC1 ZQ calibration because there is no way to triger MMDC1 ZQ.

        PHY0 ZQ_HW_PD_RES = 0x00000016

        PHY0 ZQ_HW_PU_RES = 0x00000018

        PHY1 ZQ_HW_PD_RES = 0x00000000

        PHY1 ZQ_HW_PU_RES = 0x00000000

 

4.MMDC1 Read DQS/Read delay/Write Delay calibration:
As you can see the result, the MMDC1 calibrations are fail.

=============MMDC0 calibration==================

Ending Read DQS Gating calibration. Error mask: 0x0

Starting Read Delay calibration.

Ending Read Delay calibration. Error mask: 0x0

Starting Write Delay calibration.

Ending Write Delay calibration. Error mask: 0x0

MMDC registers updated from calibration

Read DQS gating calibration:

        MPDGCTRL0 PHY0 = 0x464B0650

        MPDGCTRL1 PHY0 = 0x064C062B

Read calibration:

        MPRDDLCTL PHY0 = 0x48404842

Write calibration:

        MPWRDLCTL PHY0 = 0x312D3732

Status registers bounds for read DQS gating:

        MPDGHWST0 PHY0 = 0x04100001

        MPDGHWST1 PHY0 = 0x040b0001

        MPDGHWST2 PHY0 = 0x03eb0001

        MPDGHWST3 PHY0 = 0x040c0001

=============MMDC1 calibration==================

Ending Read DQS Gating calibration. Error mask: 0x1

Starting Read Delay calibration.

Ending Read Delay calibration. Error mask: 0x5

Starting Write Delay calibration.

Ending Write Delay calibration. Error mask: 0x1

 

5. The ddrstress tester 1.03 for lpddr2 can run perfectly for LPDDR2 calibrations, I think some configs or procedures are needed or missing for MMDC1/2x32 in uboot code. if no one can help to solve the issue, is it possible to get the source code to trace the difference, even it may work by using software calibration method.


Thank you
Andy

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