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Using FIFO Rx/TX buffers of UART

Question asked by David XY Zhou on Apr 13, 2016
Latest reply on Apr 14, 2016 by David XY Zhou

Hi,

I have K60 F120 tower. I want to use UART Rx/Tx buffers. I have setup and enable Rx/Tx as follows:

//Clear RE/TE

UART5_C2 &= (uint8_t)(~(uint8_t)(UART_C2_RE_MASK | UART_C2_TE_MASK) );

//Flush Rx/Tx FIFO Buffer

UART5_CFIFO &=(uint8_t)(~(uint8_t)(UART_CFIFO_RXFLUSH_MASK | UART_CFIFO_TXFLUSH_MASK));   

//Enable Rx/Tx FIFO Buffer

UART5_PFIFO |= ( UART_PFIFO_TXFE_MASK | UART_PFIFO_RXFE_MASK );   

//Set 128 DataWords Rx/Tx FIFO Buffer

UART5_PFIFO |= ( UART_PFIFO_RXFIFOSIZE(6) | UART_PFIFO_TXFIFOSIZE(6));

UART5_S1;                                       

//Flush Rx/Tx FIFO Buffer

UART5_CFIFO &=(uint8_t)(~(uint8_t)(UART_CFIFO_RXFLUSH_MASK | UART_CFIFO_TXFLUSH_MASK));   

//clear RXOF

UART5_SFIFO |= UART_SFIFO_RXOF_MASK;  

//Set RE/TE

UART5_C2 |= (uint8_t)(UART_C2_RE_MASK | UART_C2_TE_MASK) ;

 

I can Tx data by writing to D register:

  UART_PDD_PutChar8(UART5_BASE_PTR, pbBuffer[i]);   

 

But a few questions:

TDRE will set when the number of datawords in the transmit buffer (D and C3[T8])is equal to or less than

the number indicated by TWFIFO[TXWATER]. A character that is in the process of being transmitted is not

included in the count. To clear TDRE, read S1 when TDRE is set and then write to the UART data register

(D).

For more efficient interrupt servicing, all data except the final value to be written to the buffer must be

written to D/C3[T8]. Then S1 can be read before writing the final data value, resulting in the clearing of the

TRDE flag. This is more efficient because the TDRE reasserts until the watermark has been exceeded.

So, attempting to clear the TDRE with every write will be ineffective until sufficient data has been written.

0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].

1 The amount of data in the transmit buffer is less than or equal to the value indicated by

TWFIFO[TXWATER] at some point in time since the flag has been cleared.

 

Was confusing to me.

Put it simple: if I want to control the FIFO buffer as:

1. disable TX

2. flush FIFO buffer ( may be not necessary, if I know how much is left in the FIFO)

3. put all data into FIFO

4. then go (for transmitting)

5. When Done TX, interrupt triggers.

 

Thank you,

David Zhou

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