The Hardware Development Guide for Vybrid, Rev. 1, 05/2015 says in Table 20 on page 36 that the reference length for the DDR_CLK differential pair is 3 inches. Do they have to be this long? The Guide recommended that the traces be as short as possible in other places. Can we route the DDR_CLK differential pair 1 inch or 800 mils?
Also, what strategy does Table 22 on page 39 show, same-length or by-byte group? Thank you.