I need some precision about JTAG scan chain.
I'm misunderstanding what is the device which halt/run the CPU during a JTAG debug session.
For example when I connect a JTAG debug tool to the JTAG pins, which device on the JTAG daisy-chain enable to read the CPU registers or halt it ?
In the document IMX6SDLRM, Rev. 2, 04/2014:
It is explaned (p. 364/5829):
"The SJC module is the bridge between external development and test instrumentation and
the internal JTAG-accessible debug and test resources."
An overview of the JTAG architecture is given(p. 4914/5829)
On the JTAG daisy-chain there are in particular 2 devices :
- The OnCE (On chip Emulator) of the SDMA
- The DAP (Debug Acces Port)
It is explained (p.366/5829) :
"The SDMA debug features are primarily defined by the OnCE portion of its design."
Please, I need some precision:
[Q1] Does the OnCE portion is used for debugging only the SDMA 32-bit RISC processor ?
[Q2] If I want to halt Cortex-A9 core, read its registers this is the DAP module which work on the JTAG chain ?
Thank you for any help.