We have a project where we use SPI protocol to allow the communication between two microcontrolers. We use a MC9S12XET256 as slave.
On this last microcontroller, the SPI data are loaded on transmission interruptions (Rx and Tx interruptions are allowed). What we saw with the SPI analyser, is we have a shift of two bytes... We understand well the first one, it's because we loaded our first byte in the transmitter buffer after receiving the first byte from the master. But we can not explain the second shift...
After reading the datasheet, it is as we have a data buffer between SPI Data Register and Shifter... Can you confirm this behaviour?