Hi imx6 friends,
I'm trying to get the mxc_epdc_fb driver to work for me on a 6sl board running 3.14.28. The driver loads properly but when it tries to do the first update, I can see that the timing is not correct. Putting debug in the code, I can see that the driver is trying to set the pix clk to 40MHz (which is the right value) but seems to end up with an unreasonable value of 324MHz as the clk_set_rate fails:
imx_epdc_fb 20f4000.epdc: 5214: clk_set_rate on pix clk gave err=-16, ebusy=16
imx_epdc_fb 20f4000.epdc: 5217 rate set on pix clk rounded=40000000, target=40000000, actual=324999996
which comes from:
clkret = clk_set_rate(fb_data->epdc_clk_pix, rounded_pix_clk);
if (clkret < 0) {
dev_dbg(fb_data->dev, "%d: clk_set_rate on pix clk gave err=%d, ebusy=%d\n", __LINE__, clkret, EBUSY);
}
dev_dbg(fb_data->dev, "%d rate set on pix clk rounded=%d, target=%d, actual=%d\n", __LINE__, rounded_pix_clk, target_pix_clk, clk_get_rate(fb_data->epdc_clk_pix));
looking at the CCF drivers/clk/clk.c implementation, it looks like EBUSY is returned if the prepare count is non-zero.
1526 if ((core->flags & CLK_SET_RATE_GATE) && core->prepare_count)
1527 return -EBUSY;
I'm debugging further now to find out whether something else has already enabled pix clock. But I'm also suspicious whether anything needs to be done to the device tree script for imx6sl-evk. I don't see any mention of axi or pix clock in the epdc definition.
&epdc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_epdc_0>;
V3P3-supply = <&V3P3_reg>;
VCOM-supply = <&VCOM_reg>;
DISPLAY-supply = <&DISPLAY_reg>;
status = "okay";
};
Does there need to be something like:
clocks = <&clks IMX6SL_CLK_CSI>;
clock-names = "csi_mclk";
which I see is present for i2c.
I have attached my devicetree file.
I'd appreciate any advice/suggestions on this.
Thanks!
Original Attachment has been moved to: imx6sl-evk.dts.zip
