It is a question about CA5_WDGRST_MASK.

[soichiyamamoto]

Hi,

It is a question about CA5_WDGRST_MASK.

Q1)

I think that I can mask reset of WDOG by the following description of ReferenceManual.

Is it right?

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7.3.3.2 SRC Control Register (SRC_SCR)

CA5_WDGRST_MASKの説明

Mask CA5 WDOG reset. If these 4 bits are coded from A to 5 then,

CA5 WDOG reset input to SRC will be masked and will not reset the

1. device. Any other code will be coded to 1010 and CA5 WDOG reset will

not be masked

NOTE:

During the time the WDOG event is masked using SRC logic, it is likely

that WDOG Reset Status Register (WRSR) bit 1 (which indicates WDOG

timeout event) will get asserted.

SW / OS developer must prepare for this case.

Re-enable WDOG is possible, by un-mask it in SRC, though it must be

preceded by servicing the WDOG.

However, for the case that the event has been asserted, the status bit

(WRSR bit-1) will remain asserted, regardless of servicing the WDOG

1. module.

(HW reset is the only mean to cause de-assertion of that bit).

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Q2)

I think that time needs it for WDT refreshment from the constitution of the clock of WDOG.

I attached a figure of sequence. I confirm it, and please tell me whether recognition is right.

Best regards,

soichi

[jiri-b36968 · Accepted solution]

Hello Soichi-san,

1. yes, using this mask bit you can mask WDOG event. So if WDOG times out, the event does not go into SRC and SoC RESET is not asserted.

2. Generally it is right. Some time is needed to change state of internal logic gate in SRC which masks WDOG event. It takes couple of platform and then peripheral clocks. Usually we use higher clock than 24MHz. WDOG uses internal timer and honestly I'm not sure if it is 32kHz. Timeout event is defined in half of seconds. We can presume that decision is made every half of second.

/Jiri