It is a question about CA5_WDGRST_MASK.
I think that I can mask reset of WDOG by the following description of ReferenceManual.
Is it right?
126.96.36.199 SRC Control Register (SRC_SCR)
Mask CA5 WDOG reset. If these 4 bits are coded from A to 5 then,
CA5 WDOG reset input to SRC will be masked and will not reset the
- device. Any other code will be coded to 1010 and CA5 WDOG reset will
not be masked
During the time the WDOG event is masked using SRC logic, it is likely
that WDOG Reset Status Register (WRSR) bit 1 (which indicates WDOG
timeout event) will get asserted.
SW / OS developer must prepare for this case.
Re-enable WDOG is possible, by un-mask it in SRC, though it must be
preceded by servicing the WDOG.
However, for the case that the event has been asserted, the status bit
(WRSR bit-1) will remain asserted, regardless of servicing the WDOG
(HW reset is the only mean to cause de-assertion of that bit).
I think that time needs it for WDT refreshment from the constitution of the clock of WDOG.
I attached a figure of sequence. I confirm it, and please tell me whether recognition is right.