About the RX FIFO memory size(in page 1678 of IMX28 RM pdf)
25.3.1 Rx FIFO Structure
When the FEN bit is set in the MCR, the memory area from $80 to $FF (which is
normally occupied by MBs 0 to 7) is used by the reception FIFO engine. Table 25-4
shows the Rx FIFO data structure. The region $0-$C contains a MB structure which is the
port through which the CPU reads data from the FIFO (the oldest frame received and not
read yet). The region $10-$DF is reserved for internal use of the FIFO engine. The region
$E0-$FF contains an 8-entry ID table that specifies filtering criteria for accepting frames
into the FIFO. Table 25-5 shows the three different formats that the elements of the ID
table can assume, depending on the IDAM field of the MCR. Note that all elements of the
table must have the same format. See Rx FIFO for more information.
I don't know how to define the memory size of RX FIFO register.