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Setting incoming interrupt from micrel ksz9021rn to GPIO

Question asked by Roberto Fichera on Apr 6, 2016
Latest reply on Apr 7, 2016 by igorpadykov


Hi All,

 

I've an iMX6Q custom board using a micrel ksz9021rn gigabit ethernet, mostly working ok. However I'm now looking how to feed the INT_N interrupt output pin to the SoC ENET_RXD1 pin in order to set correctly the GPIO01_IO26 as input interrupt to the PHY. I know that my DTS has to be set as:

 

&fec {

  pinctrl-names = "default";

  pinctrl-0 = <&pinctrl_enet>;

  phy-mode = "rgmii";

  phy-reset-gpios = <&gpio1 25 0>;

  txen-skew-ps = <0>;

  txc-skew-ps = <3000>;

  rxdv-skew-ps = <0>;

  rxc-skew-ps = <3000>;

  rxd0-skew-ps = <0>;

  rxd1-skew-ps = <0>;

  rxd2-skew-ps = <0>;

  rxd3-skew-ps = <0>;

  txd0-skew-ps = <0>;

  txd1-skew-ps = <0>;

  txd2-skew-ps = <0>;

  txd3-skew-ps = <0>;

  interrupts-extended = <&gpio1 26 IRQ_TYPE_LEVEL_HIGH>,

       <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;

  status = "okay";

};

 

interrupt-extended is actually commented out because doesn't work and end up in a kernel crash. My current iomuxc is set has below

 

    janas-imx6q {

        pinctrl_enet: enetgrp {

            fsl,pins = <

                MX6QDL_PAD_ENET_MDIO__ENET_MDIO     0x100b0

                MX6QDL_PAD_ENET_MDC__ENET_MDC       0x100b0

                MX6QDL_PAD_RGMII_TXC__RGMII_TXC     0x100b0

                MX6QDL_PAD_RGMII_TD0__RGMII_TD0     0x100b0

                MX6QDL_PAD_RGMII_TD1__RGMII_TD1     0x100b0

                MX6QDL_PAD_RGMII_TD2__RGMII_TD2     0x100b0

                MX6QDL_PAD_RGMII_TD3__RGMII_TD3     0x100b0

                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x100b0

                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0

                MX6QDL_PAD_RGMII_RXC__RGMII_RXC     0x1b0b0

                MX6QDL_PAD_RGMII_RD0__RGMII_RD0     0x1b0b0

                MX6QDL_PAD_RGMII_RD1__RGMII_RD1     0x1b0b0

                MX6QDL_PAD_RGMII_RD2__RGMII_RD2     0x1b0b0

                MX6QDL_PAD_RGMII_RD3__RGMII_RD3     0x1b0b0

                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0

                /* Phy reset */

                MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25  0x000b0

                /* Interrupt */

                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26    0x000b1

            >;

        };

 

I know the setup of RXD1__GPIO1_IO26 is wrong because I'll have to force SION bit for it. Then I looked at imx6q sabrelite implementation that uses this #define below to specify the iomuxc for the same purpose.

 

#define MX6QDL_PAD_GPIO_6__ENET_IRQ         0x230 0x600 0x03c 0x11 0xff000609

 

So my question is what is the 0x03c SELECT_INPUT register since I don't find it in the reference manual?

In my case likely I'll have to setup my GPIO1_IO26 as below and replace MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 with the new MX6QDL_PAD_ENET_RXD1__ENET_IRQ:

 

#define MX6QDL_PAD_ENET_RXD1__ENET_IRQ            0x1e0 0x4f4 ???? 0x11 0xff000609 (???)

 

But I'm not sure about the 3rd param and if the 5th looks correct or not.

 

Any one can help?

 

Thanks in advance,

Roberto Fichera.

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