I'd like to reset i.MX6Q without resetting PF0100 and implemented the design.
However when only i.MX6Q is reset, we got lower VDDARM_IN output(about 960mV) from PF0100.
I guess thanks to DVFS, i.MX6Q can operate in lower frequency and lower voltage.
When i.MX6Q is reset in such situations, PF0100 continues to provide the lower voltage even though i.MX6Q needs more voltage in reset. Is this correct understanding?
I found reset(SW2) is directly connected to PMIC in the current SabreSD design.
I also found the following design in the old SabreSD schematics.
From the NOTE, there seems to have been troubles resetting i.MX6Q without getting reset de-asserted from the PMIC.
What's the issue?
Is it possible to create a design that only resets i.MX6Q but resets PF0100?