CPU Core Revision
The CPU core revision level is identified in the System Control Block (SCB) by the CPUID register found at address 0xE000ED00. Further information can be found in ARM’s Device Generic User Guide.
ARM defines the structure of this register for each CPU variant.
The following devices are provided for reference.
LPC812 r0p0 Cortex-M0+
LPC1768 r2p0 Cortex-M3
LPC1788 r2p0 Cortex-M3
LPC1837 r2p1 Cortex-M3
LPC1850 r2p1 Cortex-M3
LPC4357 r0p1 Cortex-M4F
When debugging under the Keil uVision IDE, enterring "SCB" in the Memory1 view will display the contents of the CPUID register.