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QorIQ GPIO Input Buffer Enable register support

Question asked by ROB WESTFALL on Mar 31, 2016
Latest reply on Apr 7, 2016 by ROB WESTFALL

In the Rev1 version of the T1040 Reference manual, the GPIO block got a new register - The "GPIO Input Buffer Enable Register (GPIOx_GPIBE)".  This was not in the older RevE manual.  The manual says this:

     The GPIO Input Buffer Enable register is used to control the input enable of each

     individual GPIO port. When an individual GPIO port’s direction is set to input

     (GPIO_GPDIR[DRn=0]), the associated input enable must be set (GPIOxGPIE[IEn]=1)

     to propagate the port value to the GPIO Data Register. When a port’s input enable is

     disabled, the port value does not propagate to the GPIO Data Register.


What CPU version was this implemented in? And what happens if I don't set them.  The documentation says that a value of zero makes the port disabled, and the reset value for the register is all zero's, meaning all inputs are disabled.


We are building a new CPU board that uses the T1042 cpu, and I'm confused about what happens here.  I am working off the T1040RDB, but it doesn't actually use any GPIO so it doesn't help me.

The latest UBoot software does not have this register in their register mapping headers.



Rob Westfall

Xerox Corporation