We assigned protocol (0x16) to configure the lanes for PCIe with SerDes on the QorIQ configuration tools. The bit settings in RCW to control the power-down are correct, and we can see the bank 1 (where the PCIe lands use) is powered. However I noticed that PD bit was set SRDS1_B1GCRn0 for lane C of Bank1, and PD bit was not set for lane D. My question is that why the Power-down bit is set in the SRDS1_B1GCRn0? Even thought the lane was not set to power-down in the RCW? If I attempt to clear the PD bit, will that put the lane in power-up state?