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i.MX6SL LPDDR2 instability

Question asked by Tom Rini on Mar 25, 2016
Latest reply on May 23, 2016 by Raul Benet

Hey all.  I have a product that is heavily based on the i.MX6SL EVK.  Our currently shipping (> 100k units) make use of the MT42L256M32D2LG-25 part from Micron (which is a very slight variation on the part used on the EVK).  As this part reaches EOL next year, we're looking at the EDB8132B4PM-1D-F-D from Micron, at Micron's suggestion.  They have confirmed that this part is pin-compatible, and based on the datasheets, it should be software compatible too.  We have around 10 units with the new DDR part and all of them fail, in different ways.  We've enlisted Micron's help and they have noticed a number of JEDEC violations during the init sequence.  There's two big questions I wonder if anyone can help with.

 

First, while we're based on imx_v2009.08_12.10.02 I've reproduced these with imx_3.14.52_1.1.0_ga and the mx6slevk build.  One problem is that the default write value to MMDC_MDOR is not at all right (it doesn't set the values required by the JEDEC spec), the value seems to be ignored.  I've changed the value over to 0x10, but the observed wait time, both with that value and with 0x20E, is around 280 nanoseconds, not the required 200 microseconds (so we're off by a few orders of magnitude!).  The second is that any write to MMDC_MPWRCADL results in a failure to boot from SD.  What is very strange about this is that I can use imx_usb to boot these images (and Micron has as well, and measured that adding maximum delay here almost fixes some other violations that were noted).

 

Any ideas?  Thanks!

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