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If I lock L1 I cache of MPC7410 ...

Question asked by Yongsung Kwon on Mar 25, 2016
Latest reply on Mar 29, 2016 by LPP

If I lock L1 I cache(with L1 I and L1 d cache enabled, L2 disabled) of MPC7410, does system bus transaction occur same as when L1 I cache unlocked? Does 32-byte burst read occur?


I have encountered system crash when a certian event occur with L1 I, LI D cache eabled, L2 disabled.

But system does not crash with L1 I cache disabled.


I have been suggested to do intense memory test with L1 cache locked from a fellow engineer.

Doing that, would bus operation still be heavy same as L1 cache unlocked?

If system does not crash with L1 I cache locked, Can I conclude that bus line transaction(ex. burst read) has no problem?