NXP recommendation for the layout of the DDR3 with
a two chip solution is to use a balanced T for the clock, address, and command
lines, which is how it is implemented on the Saber board. In
the NXP layout recommendations, you list the lengths of each of the
groups. In particular, you list the max length of the clock traces to be
no greater than 2.25 inches. In a balanced T configuration, does this
consider the total length of the T (both branches), or is it the distance from
the iMX6 to a DDR3 pad?
The reason customer is asking is that they conform to the latter
but not the former. Any thoughts/advice/suggestions?