I consider the Flexbus read timing .
In figure 13. FlexBus read timing diagram of K64P144M120SF5 rev6,About Flexbus timing,
the time from CLK_RISE to FB_OE (control signals) is covered by the FB3 spec,
the time from CLK_RISE to input Date hold time spec is FB5.
FB3 is 0 ns (Min).
FB5 is 0.5 ns (Min).
I connect the flash memory to Flexbus.
The flash memory AC timing is as follows.
OE# to output transition is 0 ns (Min).
In the case of without including board delay, the Hold time is not enough for MCU read timing.
Is it possible to ensure the hold time by setting a register (Chip Select Control Register ...) ?
I hope to use in "AA = 1" (Auto-Acknowledge Enable ) setting .