Is there a way to test powerpc L1 instruction cache's health at the assembly or c code level?

[yongsungkwon]

Is there a way to test powerpc L1 instruction cache's health at the assembly or c code level?

My system has mpc7410 with L1 instruction and L1 data cache enabled.

My system stop running when a cetain even(I guess at that time Instruction excution flow changes much) occurs with L1 cache enabled.

I found that my system does not corrupt with L1 cache disabled!

So I would like to know L1 cache is healthy or not, especially for L1 Instruction cache.

Thank you in advance! 

[yongsungkwon]

I deeply thank you for your answer.

>Parity errors cause machine check exception and you would get this exception in the case of error.

  I checked MSR ME bit when my system corrupted, it had '1'. If machine check exception occurs, ME bit has '0' ? right?

>My suggestion is to perform a intense memory testing with the test code locked in L1 Icache.

   I have done external 8Mbytes SRAM full test with WindProbe emulator and Workbech Debug Hardwarediagonostics function when my system corrupted. Full SRAM test has passed three time, it takes about 30 minuites.

   Could you tell me more how to perform a intense memory testing with the test code locked in L1 I cache?

Thank you in advance!

Have a good day,

Yongsung Kwon

[LPP]

1. You can provide hooks at all exceptions to catch if any raised.

Indeed, ME is cleared at machine check.

However, you might get a different exception (program exception on wrong fetch). In this case, ME is not altered.

2. Debug hardware diagnostic is a functional test and it is not a stress test.

Use an optimized  memory copy with enabled L1 I/D caches.

[LPP]

>Is there a way to test powerpc L1 instruction cache

L1 instruction cache is protected by one parity bit per instruction, no parity checking on tags. Parity errors cause machine check exception and you would get this exception in the case of error.

The only way to get data values into the instruction cache is to fetch them as instructions from memory into the L1 i-cache. To test the values, they must be executed as instructions. There is no way to run pattern type test through the L1 i-cache.

>my system does not corrupt with L1 cache disabled

Typically, this behaviour is the indication of problems on system bus or external memory. When L1 Icache is disabled then most transactions from the core are sparced and may not cause issues whereas enabling L1 cache makes dense activities on the bus.

My suggestion is to perform a intense memory testing with the test code locked in L1 Icache.

Have a great day,
Pavel

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