I have a collection of Kinetis K10 50MHz uCs connected via I2C. I am (ab)using the I2C bus to read their interrupt states back as a bitfield by using the dominant and recessive nature of the 0 and 1 bits on the I2C bus.
I first attempted to do this using address 0, as that was already set up as my 'global' address. The reads did not act as expected, with the bus getting stuck after reading the expected number of bytes. The master did/could not generate the STOP condition.
I believe I have ruled out the slaves holding the bus as I did not set up a read on the slave, so the slave transmitted the fill byte, but I am not entirely sure. I could break the I2C connection during the stuck state to determine which uC is at fault.
Changing the address on the master and all slaves to 7Fh resolved the problem.
Is there something in the I2C hardware that does not handle a read from address 0?