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iMX6 GPIO state during Startup & Power Sequencing

Question asked by Sonu Kurian on Mar 18, 2016
Latest reply on Mar 30, 2016 by Sonu Kurian

Hello All,

 

We have a custom board based on i.MX6 (Quad), processor: IMX6 Quad, revision: C. It is powered from PMIC PF0100. We found glitches on few GPIO lines (Ball Name: DI0_PIN2, Ball No: N25) during start up and also noticed that these glitches have relation to power sequencing.

Scenario 1:

Following is the power sequence:

  1. VDDARM_IN, VDDSOC_IN
  2. NVCC_XXX lines
  3. NVCC_DRAM
  4. VDD_SNVS_IN, VDDHIGH_IN

On this sequence we see a glitch (unwanted toggling) on the DI0_PIN2 during start up. Please see the attached waveform

Scenario 2:

Following is the power sequence:

  1. VDD_SNVS_IN
  2. VDDARM_IN, VDDSOC_IN
  3. NVCC_XXX lines, VDDHIGH_IN
  4. NVCC_DRAM

On this sequence we see no glitch but the pin DI0_PIN2  which should be a HIGH due to internal 100K pull up becomes so only after a few milli seconds from RESET.

Scenario 3:

Following is the power sequence:

  1. VDD_SNVS_IN, VDDHIGH_IN
  2. VDDARM_IN, VDDSOC_IN
  3. NVCC_XXX lines,
  4. NVCC_DRAM

 

On this sequence we see no glitch and pin DI0_PIN2 becomes HIGH before release of RESET.

 

Observation from above scenarios: VDD_SNVS_IN and VDDHIGH_IN should be applied to i.MX6 before any other supply rails for a glitch free GPIO transitions during reset.

Datasheet says “VDD_SNVS_IN” should be applied first. But I think not anything about “VDDHIGH_IN”.

 

Is my observation expected?

What is the dependency of GPIO pin on VDD_HIGH_IN?

 

Thanks in Advance!

 

Regards,

Sonu Kurian

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