KL17 Bit SPMF in the SPIx_S field

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KL17 Bit SPMF in the SPIx_S field

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fireman
Contributor I

On behalf of my customer:

At the SPI in the KL17 my customer has found a discrepancy, versus the KL25. I is the Bit SPMF in the SPIx_S field.

- KL17P64M48SF2RM manual page 502

- KL25P80M48SF0RM manual page 666

In both reference manuals is the statement: "To clear the flag, read SPMF when it is set and then write a 1 to it."

In the file MKL17Z4.h is "S" only defined for reading:

/** SPI - Register Layout Typedef */

typedef struct {

__I uint8_t S; /**< SPI Status Register, offset: 0x0 */

At the KL25 file for read and write:

/** SPI - Register Layout Typedef */

typedef struct {

__IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */

__IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */

__IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */

__IO uint8_t S; /**< SPI status register, offset: 0x3 */

If one does a correction in the KL17 file to__IO, then compiling works, but the file isn't original any longer... :smileysad:

If one keeps the S-Register as only read, one gets during the compilation an error: "assignment of read-only member 'S' SPI0->S |= 0x40;"

My customer thinks the .h-File is wrong and the reference manual is correct.

In both reference manuals is written under SPI status register (SPIx_S): "This register contains read-only status bits. Writes have no meaning or effect."

But in the flowcharts is the statement: READ SPMF WHILE SET TO CLEAR FLAG, THEN WRITE A 1 TO IT

Best regards,

Marno Friebe

Senior Field Application Engineer

EBV Elektronik GmbH & Co. KG

Marno.Friebe@ebv.com<mailto:Marno.Friebe@ebv.com>

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3 Replies

1,905 Views
Hui_Ma
NXP TechSupport
NXP TechSupport

Hi

As the reference manual shows to clear SPMF bit in SPI0_S register need read SPMF when it is set and then write a 1 to it.

Please refer below SPI interrupt code for KL25 product SPI module validation:

if ((SPI0_S & SPI0_S_SPMF_MASK)&&(SPI0_C2 & SPI0_C2_SPMIE_MASK))     //SPI match interrupt

    {

   SPI0_S |= SPI0_S_SPMF_MASK;
    printf("SPI0 match interrupt\n");
  

}


Wish it helps.

Have a great day,
Ma Hui
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1,905 Views
fireman
Contributor I

Hello Hui Ma,

thanks for your answer! My customer programmed the SPI's similar to your solution.

But that isn't the main point. The manuals and the provided MKL17Z4.h - files do not match!

Where can this documentation and SW discrepancy be addressed to avoid the same pitfalls at other customers?

Best regards,

Marno

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1,904 Views
Hui_Ma
NXP TechSupport
NXP TechSupport

Hi

I checked the updated KSDK V2.0 MKL17Z4.h with below SPI register type definition:

/** SPI - Register Layout Typedef */

typedef struct {

  __IO uint8_t S;                                  /**< SPI Status Register, offset: 0x0 */

  __IO uint8_t BR;                                /**< SPI Baud Rate Register, offset: 0x1 */

The updated <MKL17Z4.h> file has fixed the issue.

Please check attached file for the detailed info.


Wish it helps.

Have a great day,
Ma Hui
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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