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imx6sx DDR cacheability

Question asked by catalinzafiu on Mar 18, 2016
Latest reply on Apr 6, 2017 by johne smith

Hello Everybody,


I have a bare-metal code running on M4 core.

The core executes, from DDR, much slower than expected, that means more than 10 times slower than executing from TCM.


I suspect the cache is not properly configured.

The cache controller is enabled using the LMEM_EnableSystemCache() and LMEM_EnableCodeCache() provided by NXP on FreeRTOS example.There is no effect for execution time after calling LMEM functions.

I did not find anything about cacheability.

Is there any way to define/check the DDR cacheability for M4? I mean to define DDR regions as cacheable/non-cacheable.