I consider a Watchdog Timer (WDOG) behavior in the on-chip boot ROM code.
In figure 8-2 Serial Download Boot Flow of IMX6DQRM Rev. 3,
it said ARM core will reset if no any activity within 90 seconds when WDOG_ENABLE=1.
do the WDOG External signals ( WDOGx_B ,WDOGx_RESET_B_D ) connect to iMX6 I/O pad ?
which pads are connected with WDOG External signals ?
DISP0_DAT8 or GPIO_9 or SD1_DATA2 or DISP0_DAT9 or GPIO_1 or SD1_DATA3