MQX 4.2 Vybrid A5 SAI2 SGTL5000

[McuG]

We are trying to bring up a new board based on a Vybrid , using MQX 4.2, the A5 tower version of the bsp. We are having some difficulties when configuring the SAI2 port to interface to the SGTL5000 chip (for audio playback) that we have on board.

Could someone take a look at the configuration and point out if something is missing,  at this point we do not see the SYS_MCLK     being generated onto thePTB18 and the I2C communication with the SGTL5000 fails due to this

We are using as a reference the sai_dma_demo project and we updated the bsp to accommodate our connections:

SGTL5000       <->           Vybrid

SYS_MCLK     <-> EXT_AUDIO_MCLK (PTB18)

I2S_SCLK        <-> SAI2_TX_BCLK (PTC12)

I2S_LRCLK      <-> SAI2_TX_SYNC (PTC17)

I2S_DIN            <-> SAI2_TX_DATA (PTC15)

I2S_DOUT        <-> SAI2_RX_DATA (PTC14)

_bsp_sai_io_init:

.....

case 2:

        // RX_BCLK          

            IOMUXC_PTC13 = IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(5) | IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;

            // RX_DATA

            IOMUXC_PTC14 = IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(5) | IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;

            // RX_SYNC

            IOMUXC_PTC16 = IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(5) | IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;

            // TX_SYNC

            IOMUXC_PTC17 = IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(5) | IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(7) | IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(1) | IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK | IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK | IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK;

            // TX_DATA

            IOMUXC_PTC15 = IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(5) | IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(7) | IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(1) | IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK | IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK | IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK;

            // TX_BCLK

            IOMUXC_PTC12 = IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(5) | IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(7) | IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(1) | IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK | IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK | IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK;

           //MCLK

            IOMUXC_PTB18 = IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(2) | IOMUXC_SW_MUX_CTL_PAD_PAD_SPEED(3) | IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK;

            // select clock source

            CCM_CSCMR1 = (CCM_CSCMR1 & ~CCM_CSCMR1_SAI2_CLK_SEL_MASK) | CCM_CSCMR1_SAI2_CLK_SEL(3);

            CCM_CSCDR1 = (CCM_CSCMR1 & ~CCM_CSCDR1_SAI2_DIV_MASK) | CCM_CSCDR1_SAI2_DIV(0x0f);

            CCM_CSCDR1 |= CCM_CSCDR1_SAI2_EN_MASK;

            // enable SAI2 clock

            CCM_CCGR1 |= CCM_CCGR1_CG1(0x3);

     break

clocks_init:

.....

// SAI2

    CCM_CSCMR1 = (CCM_CSCMR1 & ~CCM_CSCMR1_SAI2_CLK_SEL_MASK) | CCM_CSCMR1_SAI2_CLK_SEL(3);  // SAI2 clk src PLL4

    CCM_CSCDR1 = (CCM_CSCDR1 & ~CCM_CSCDR1_SAI2_DIV_MASK) | CCM_CSCDR1_SAI2_DIV(6 - 1);      // SAI2 clk div 6 -> final freq 1179.648 / 16 / 6 = 12,288MHz

    CCM_CSCDR1 |= CCM_CSCDR1_SAI2_EN_MASK;                                                   // enable SAI2 clk

    I2S2_TCR2 = I2S_TCR2_MSEL(1);

.....

KSAI_INIT_STRUCT _bsp_ksai_init = {

    2,                           /* Selected peripheral (HW channel) */

    0,                           /* TX channel */

    0,                           /* RX channel */

    I2S_TX_ASYNCHRONOUS |        /* TX is asynchronous */

    I2S_RX_SYNCHRONOUS |         /* RX hooked on TX */

    I2S_TX_BCLK_NORMAL  |        /* Both TX and RX are clocked by the transmitter */

    I2S_RX_BCLK_NORMAL,          /* bit clock (SAI_TX_BCLK) */

    I2S_TX_MASTER |              /* SAI transmitter mode */

    I2S_RX_SLAVE,                /* SAI receiver mode */

    I2S_CLK_INT,                 /* Clock source */

    5,                           /* Interrupt priority */

    4,                           /* Buffer block number */

    512,                         /* Buffer size */

    CM_CLOCK_SOURCE_PLL_AUDIO,   /* Internal master clock source */

    &_bsp_audio_data_init        /* Audio init */

};

InitCodec:

...

uint8_t mode = (I2S_TX_MASTER | I2S_RX_SLAVE);

i2s_ptr = fopen("sai:", "w");

ioctl(i2s_ptr, IO_IOCTL_I2S_SET_MODE_MASTER, &mode);

ioctl(i2s_ptr, IO_IOCTL_I2S_SET_MCLK_FREQ, &mclk_freq);

...

[McuG · Accepted solution]

We managed to address it by configuring PTB18 as O1, making the clock available to SGTL5000 SAI2 was reconfigured to use internal clock. Next step is to enable PLL for SGTL5000

As a  reference, our question is similar to https://community.freescale.com/thread/317985

case 2:

            // RX_BCLK        

            //IOMUXC_PTC13 = IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(5) | IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;

            // RX_DATA

            IOMUXC_PTC14 = IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(5) | IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;

            // RX_SYNC

            //IOMUXC_PTC16 = IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(5) | IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;

            // TX_SYNC

            IOMUXC_PTC17 = IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(5) | IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(7) | IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(1) |

                            IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK | IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK | IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK;

            // TX_DATA

            IOMUXC_PTC15 = IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(5) | IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(7) | IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(1) |

                            IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK | IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK | IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK;

            // TX_BCLK

            IOMUXC_PTC12 = IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(5) | IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(7) | IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(1) |

                            IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK | IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK | IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK;

            // EXT_AUDIO_MCLK

            IOMUXC_PTB18 = IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(4) | IOMUXC_SW_MUX_CTL_PAD_PAD_SPEED(3) | IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK | IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(7);

            CCM_CCOSR = CCM_CCOSR_CKO1_EN_MASK | CCM_CCOSR_CKO1_DIV(5) | CCM_CCOSR_CKO1_SEL(7);

            // select clock source

            CCM_CSCMR1 = (CCM_CSCMR1 & ~CCM_CSCMR1_SAI2_CLK_SEL_MASK) | CCM_CSCMR1_SAI2_CLK_SEL(3);

            CCM_CSCDR1 = (CCM_CSCMR1 & ~CCM_CSCDR1_SAI2_DIV_MASK) | CCM_CSCDR1_SAI2_DIV(0x0f);

            CCM_CSCDR1 |= CCM_CSCDR1_SAI2_EN_MASK;

            // enable SAI2 clock

            CCM_CCGR1 |= CCM_CCGR1_CG1(0x3);      

            break;

KSAI_INIT_STRUCT _bsp_ksai_init = {

    2,                           /* Selected peripheral (HW channel) */

    0,                           /* TX channel */

    0,                           /* RX channel */

    I2S_TX_ASYNCHRONOUS |        /* TX is asynchronous */

    I2S_RX_SYNCHRONOUS |         /* RX hooked on TX */

    I2S_TX_BCLK_NORMAL  |        /* Both TX and RX are clocked by the transmitter */

    I2S_RX_BCLK_NORMAL,          /* bit clock (SAI_TX_BCLK) */

    I2S_TX_MASTER |              /* SAI transmitter mode */

    I2S_RX_SLAVE,                /* SAI receiver mode */

    I2S_CLK_INT,                 /* Clock source */

    5,                           /* Interrupt priority */

    4,                           /* Buffer block number */

    512,                         /* Buffer size */

    CM_CLOCK_SOURCE_PLL_AUDIO,   /* Internal master clock source */

    &_bsp_audio_data_init        /* Audio init */

};

[SergioSolis]

Thank you for posting how it was fixed McuG, it will help the community!