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imx6q pcie phy writel error

Question asked by liang jiang on Mar 15, 2016

Our solution to using an external reference 100M for PCIe has three parts:

  1. 1. Configure the CLK pins to accept a clock as input.
  2. 2. Bypass the ENET PLL, using the CLK pins as the alternate source.
  3. 3. Configure the PCIe PHY to accept a clock other than 125 MHz.

So i should set  PCIe PHY MPLL config: multiplier = 25, clkdiv2 = 0

but when i run at     writel(temp_wr_data, dbi_base + PHY_CTRL_R);   zhe system is die

static int pcie_phy_cr_cap_addr(int addr)

{

        u32 temp_wr_data;

        printk("jll   %s,%d\n",__func__,__LINE__);

        /* write addr */

        temp_wr_data = addr << PCIE_CR_CTL_DATA_LOC ;

        printk("jll  %s,%d\n",__func__,__LINE__);

        writel(temp_wr_data, dbi_base + PHY_CTRL_R);

~       ........

}      

Original Attachment has been moved to: pcie.c.zip

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