After power on the FXOS8700CQ, is the SCL/SDA pin hign or low at the first??
Once set for I2C operation (SA0 pin connected to GND or VDDIO), both the SDA nad SCL pins will be in a high impedance state, so with pull-up resistors on the bus, the SDA and SCL lines are both high.
PS: If my answer helps to solve your question, please mark it as "Correct". Thank you.
Dear Tomas Vaverka,
Thanks for your answer, my last problem have been insolved but I have another question now.
I have made the bus pulled up with 4.7KΩ resistors, and the SDA and SCL both are hign when I reset FXOS8700CQ, so do INT1 and INT2, and I made the SDA0、SDA1 connected to GND. The question is the master can give the ST singal、 slave address and write bit correctly , but the slave(FXOS8700CQ) just cann't send the ACK to the master , so the register value cann't be read or write .
First I guess that if the FXOS8700CQ doesn't work , but the INT1 and INT2 bins are both hign , while after I power it off they are both low ; Then the no.2 bin and no.8 bin are in a high impedance state , I don't know if it's true state or false state.
By the way , the VDD and VDDIO connected together to 3.3V
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