I want to configure codec for 8 kHz sample rate . As per datasheet , I used values as mentioned below.SYS_FS bitfield of CHIP_CLK_CTRL equal to 0x2( 48 KHz)
RATE_MODE of CHIP_CLK_CTRL equal to 0x3 (1/6 of the SYS_FS rate) .
With this configuration , I2S_LRCLK value I am getting is around 16 KHz which is almost double of the required one.
Internal PLL has been enabled with input frequency equal to 12 MHz.