K64 I2C Lines in Power Off Condition

[kevinstevens]

In my design I have two K64 processors that are connected to various peripherals. They are then connected together via UART for communication between the two. However, my question comes from the fact that they are also both connected to a shared I2C channel that goes to both processors as well as a couple other chips.

The second K64's power is controlled by the first K64. Therefore, there are instances where the second K64 will be powered down completely (not a low power mode, complete power removal). Is there going to be a leakage current issue from the I2C pullup resistors through the powered off K64 to GND?

The data sheet (K64F Rev5, 12/2014 --> Note 1 on page 7) states that the I/O pins are clamped to V_SS through an ESD protection diode. This makes me think that the answer is yes.

Would a current limiting resistor (as is suggested in the same note) be possible on an I2C bus? If so, is my below calculation correct R=(VDIO_MIN-VIN)/|IICDIO| = (3.3-0)/.005 = 660Ω

If not, what would be my options? Possibly a level translator inline on the I2C lines???

dereksnell​

[kevinstevens]

I have been looking at this a little more and am thinking that the NVT2002 would be a good option for the level translation. I would connect the B side to the the K64 that gets powered down and then tie enable to the switched power source (with a pull down to GND to force it low when the supply voltage is cut). VREFA would always have 3.3V on it and VREFB/EN would have 3.3V on it when power is switched on to the secondary K64. This would, I am hoping, result in the chip going to disabled mode when the secondary K64 gets powered down and would prevent any voltage from getting to the powered down K64.