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PGA Settling time MC9S12ZVL

Question asked by Charudatta Ingale on Mar 2, 2016
Latest reply on Mar 3, 2016 by Radek Sestak

Hi All,

I'm using the controller MC9S12ZVL Family which has PGA feature used for an ADC Value interfaced to Pressure Sensor.

 

Following are the Register configurations done

PGAEN = 1;

PGAGAIN = 0x02; /* 40x*/

PGAOFFSET = 0x00; /*Disabled OFFSET*/

/* ==== Analog Mode Operation for HVI pin (IGN_FB). ==== */

    PTAL_PTAENL = SET;             /* 1 PL0 is connected to ADC */

    PTAL_PTTEL = SET;             /* Input buffer enabled when used with analog function */

    PTAL_PTADIRL = CLEAR;         /* Input voltage divider active on analog input to ADC channel */

    PIRL_PIRL0 = 0x00;            /* ratio selected 1:6 */

    tPGA settling time given is 56us.

    Vref of ADC is 5v.

I have  2 analog signals output from the Low Pass Filter Circuits . These 2 signals are then fed into the microcontroller MC9S12ZVLA as the PGA circuit inputs.

These two inputs are given to PGA with a Settling time of 56us in between.

 

Issue: The value getting as PGA output for the inputs given is getting skewed occasionally. I guess, the settling time given to select the Inputs is not sufficient. Please suggest on this.

I tried giving 200us as settling time and the Outputs were stable.

 

I want to know is Settling time the reason for this, because in the Datasheet the typical sufficient settling time for input selection is mentioned as around 10us .

So changing it to 200us is way more than what the spec specifies right?

 

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