PGA Settling time MC9S12ZVL

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PGA Settling time MC9S12ZVL

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charudattaingal
Contributor IV

Hi All,

I'm using the controller MC9S12ZVL Family which has PGA feature used for an ADC Value interfaced to Pressure Sensor.

 

Following are the Register configurations done

PGAEN = 1;

PGAGAIN = 0x02; /* 40x*/

PGAOFFSET = 0x00; /*Disabled OFFSET*/

/* ==== Analog Mode Operation for HVI pin (IGN_FB). ==== */

    PTAL_PTAENL = SET;             /* 1 PL0 is connected to ADC */

    PTAL_PTTEL = SET;             /* Input buffer enabled when used with analog function */

    PTAL_PTADIRL = CLEAR;         /* Input voltage divider active on analog input to ADC channel */

    PIRL_PIRL0 = 0x00;            /* ratio selected 1:6 */

    tPGA settling time given is 56us.

    Vref of ADC is 5v.

I have  2 analog signals output from the Low Pass Filter Circuits . These 2 signals are then fed into the microcontroller MC9S12ZVLA as the PGA circuit inputs.

These two inputs are given to PGA with a Settling time of 56us in between.

 

Issue: The value getting as PGA output for the inputs given is getting skewed occasionally. I guess, the settling time given to select the Inputs is not sufficient. Please suggest on this.

I tried giving 200us as settling time and the Outputs were stable.

 

I want to know is Settling time the reason for this, because in the Datasheet the typical sufficient settling time for input selection is mentioned as around 10us .

So changing it to 200us is way more than what the spec specifies right?

 

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RadekS
NXP Employee
NXP Employee

Hi Charudatta,

There are two basic conditions:

1.    The minimum time for the input signal multiplexing is given by PGA to ADC settling time tPGA_settling.

2.    The rate of signal change within tPGA_settling must be small.

So, how it looks with input signal change?

I suppose for now that you measure voltages in range 1.5V..VDDA-1.5V and output voltages are in range 0.5V..VDDA-0.5V. Correct?

Did you subtract appropriate amount of Low Pass Filter Circuits time constants from setting time for avoid negative influence from this block propagation delay?

Could you please share here how did you implement this setting time?


I hope it helps you.

Have a great day,
RadekS

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