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imx6q-cpufreq driver violating the LDO voltage constraints while transitioning from one operating frequency to another.

Question asked by adeelarshad on Feb 27, 2016
Latest reply on Mar 2, 2016 by adeelarshad

While reviewing the imx6q-cpufreq driver in detail, we come up with the concern that this driver is probably violating the LDO voltage constraints while transitioning from one operating frequency to other operating frequency. Although after the transition it will meet the constraints if the operating points are correctly defined in device tree. But during the transition as the LDO regulators are set sequentially so during the transition period for some instructions cycles these constraints are violated.

 

Following are the voltage constraints that are being violated.

1). VDD_SOC_CAP and VDD_PU_CAP must be equal

2). VDD_ARM_CAP must not exceed VDD_SOC_CAP or VDD_PU_CAP by more than 50 mV (i.MX6 DQ) or 100 mV (i.MX6 SDL)

3). VDD_SOC_CAP must not exceed VDD_ARM_CAP by more than 200 mV (i.MX6 DQ only)

 

Just for reference the associativity of these LDO regulators with the voltages mentioned above.

For example during the scaling down,

VDD_SOC_CAP is set to new value first and then VDD_PU_CAP. So after setting VDD_SOC_CAP and before setting VDD_PU_CAP, they are at the different voltage levels and that is violating the 1st constraint mentioned above.

 

    /* scaling down?  scale voltage after frequency */
    if (new_freq < old_freq) {
                ret = regulator_set_voltage_tol(arm_reg, volt, 0);
                if (ret) {
                            dev_warn(cpu_dev,
                                         "failed to scale vddarm down: %d\n", ret);
                            ret = 0;
                }
                ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
                if (ret) {
                            dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
                            ret = 0;
                }
                if (!IS_ERR(pu_reg) && regulator_is_enabled(pu_reg)) {
                            ret = regulator_set_voltage_tol(pu_reg,
                                    imx6_soc_volt[index], 0);
                            if (ret) {
                                        dev_warn(cpu_dev,
                                                    "failed to scale vddpu down: %d\n",
                                                    ret);
                                        ret = 0;
                            }
                }
    }

 

But we have also observed that this code is functional on several variants of i.mx6 and does not harm the CPU/SoC.

So we are quite interested to know that if this code is not violating these voltage constraints, then how ?

One thing that comes in mind is that as the regulators move to new value in steps instead of abrupt change so that might be covering up these conditions.

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