can any one help how to do inter processor communication using SGI in arm, possibly with code
i am able to generate sgi independently to each core but i am unable to generate interrupt to other core using sgi
how can i do this ?
example SGI can be found in attached document from SDK
sect.4.4.6 Using software generated interrupts (SGIs).
Also sect.4.4.11 GIC "hello world" example, with one core completes
the main routine, it triggers the SGIn interrupt to another core.
thank you for your reply
i am giving the code what i am trying
i have done what you suggested, still its not working
i am debugging with DS5 in single core0 mode.( my debugger is not connecting in SMP mode )
i have some doughts
1) with out cpu init also SGI works right ,if already GIC initialized to other cores
1. gic init
3. register interrupt routine
4. enable interuupt(id,priority,cpu)
1. SGI to core0 i think its works fine
2) some times its working but some times its not i dont what is the problem
3) why my debugger unable to connect in SMP mode
cpu_id = cpu_get_current();
my_string("Hello from core ");
if(cpu_id == 0)
gic_send_sgi(SW_INTERRUPT_3, 2, kGicSgiFilter_UseTargetList);//interrupt to core1
if(cpu_id == 1)
// Set MAX_CPUS as desired; will be forced to no greater than actual number of cpus.
#define MAX_CPUS 2;
static unsigned int num_cpus = MAX_CPUS;
void configure_cpu(uint32_t cpu)
const unsigned int all_ways = 0xf;
// Enable branch prediction
// Enable L1 caches
// Invalidate SCU copy of TAG RAMs
// Join SMP
void obc_main(void * arg)
uint64_t start_time, done_time;
uint32_t cpu_id = cpu_get_current();
if (cpu_id == 0)
int cpu_count = cpu_get_cores();
gicTestDone = 1;
register_interrupt_routine(SW_INTERRUPT_3, my_isr);// register interrupt
enable_interrupt(SW_INTERRUPT_3, CPU_0, 0);//enable int
if (num_cpus > cpu_count)
num_cpus = cpu_count;
/* secondary cores starting */
for (i = 1; i < num_cpus; i++)
cpu_start_secondary(i, &obc_main, 0);
my_string("END of GIC Test \n\r");
gic_init_cpu();//init CPU interface
core1_cpsr &= 0xffffff7f;//set CPSR I bit
enable_interrupt(SW_INTERRUPT_3, CPU_1, 0);
gic_send_sgi(SW_INTERRUPT_3, 1, kGicSgiFilter_UseTargetList);
if you find any errors please give me the corrections
in my custom board i am distributing routines to both the cores for bare-metal applpication in SMP code
this code i have taken from SMP_PRIMES from SDK and modified according to my application
with out GIC both the cores working fine with some printf with mutex
please give reply as soon as possible
i found that it is problem of vector table mapping
one time interrupt is service but not next time
i am checking with epit time in continuous interrupt routine
can you tellme how exactly this ram vector table mapped ? and how can i verify that is correctly mapped with help of debugger
i am using from sdk startup code
please look at attached baremetal gpio interrupt example in interrupt.c
May be this works
Before that i tried with Changing Vector Base address to my vectors address in CP15 Register which is working fine
can i follow this or is it mandatory to locate ROM vectors to iRAM and write our routine to ram location.
I think in Startup.s code of SDK is doing copying of Vectors to iRAM location but its not working why ?
if i check memory view of iRAM in DS-5 Debugger, my IRQ_Handler is not mapped to memory location 0x91fff4.
Finally i Need Your Help to these tasks
1. My sabresd board unable to connect in multicore debugginrg (debugg configuration of DS-5 i selected Cortex-A9x2 SMP connection) it was showing "your debugger is unable to connect"
2. is MMU required for Baremetal application with this two cores running in SMP mode ?
and what are the minimum initialization required to run these two cores for my application
i really Thank you for your immediate response for my quiries
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