We are using P4080 processor in our project. I have a question about the DDR3 interface of the P4080. DDR3 interface has address,data,clock and control signals such as RESET,CKE(clock enable). During the initialization process of the DDR3, control signals has to be driven by the processor. So, control signals of the DDR3 are connected to the DDR3 interface of the P4080 . However, there is no RESET signal on the DDR3 interface of the P4080 . Because of that reason, this signal is driven by the FPGA. The design of the P4080DS is also like that. In this design, RESET signal of the DDR3 is also driven by the FPGA. In the DDR3 datasheet there is a section for initialization process. In this section, It is said that "CKE should be driven LOW prior to RESET# being driven HIGH". It means that, RESET signal and CKE signal have to be driven in sequence. However, As I said before, RESET signal is driven by FPGA and CKE signal is driven by P4080. How can we handle this situation without any trouble? How does the P4080DS handle this situation? Could you give us some technical support for the DDR3 initialization process,please?