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IMX6 PCIe (LVDS) Termination (Data)

Question asked by Dominic Musgrove-Wethey on Feb 25, 2016
Latest reply on Dec 14, 2016 by dougplymale

Hello

I am interfacing PCIe between IMX6 and a FPGA. I am a little confused with the coupling used for the IMX6 on the PCIe port.

 

The IMX6 clock and PCIe outputs are LVDS, the only thing the datasheet says about the LVDS I/O electrical characteristic is that it is TIA/EIA 644-A compliant.

Two questions: (This is both for the PCIe receiver not transmitter pair).

1.

TIA/EIA 644-A compliant devices MUST have a DC bias, the common mode range is +0.2 to +2.2V, therefore why do none of the reference designs have DC bias? This could exceed the absolute maximum rating of the pin (VSS - 0.5V or VCC + 0.3V) and cause damage to the device. There is nothing motioned about allowed common-mode voltage range for any pins being anything other than stated above, or any internal DC bias to these pins. Therefore it is my understanding that external DC bias is required.

 

2.

TIA/EIA 644-A compliant devices do not by default have internal 100R termination, I cannot find where stated that the PCIe inputs have internal termination, therefore why do none of the reference designs have external 100R termination?

 

Many thanks,

Dominic

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